EFR32SG23 Sub-GHz FSK Wireless SoC for Amazon Sidewalk

Low Power Wireless System-on-Chip

• ARM Cortex®-M33 (78 MHz) with DSP and FPU
• 512 kB flash program memory
• 64 kB RAM data memory
• Sub-GHz radio operationn

Low Energy Consumption

• 4.0 mA RX current at 915 MHz (50 kbps 2GFSK)
• 85.5 mA TX current @ 20 dBm output power at 915 MHz
• 26 μA/MHz in Active Mode (EM0) at 39.0 MHz
• 1.2 μA EM2 DeepSleep current (16 kB RAM retention and RTC running from LFRCO)

Wide Selection of MCU peripherals

• 16-bit Analog to Digital Converter (ADC)
• 2 × Analog Comparator (ACMP)
• 2 x Digital to Analog Converter (VDAC)
• Low-Energy Sensor Interface (LESENSE)
• 23 General Purpose I/O pins
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM channels
• 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM channels
• 32-bit Real Time Counter
• 24-bit Low Energy Timer for waveform generation
• 16-bit Pulse Counter with asynchronous operation (PCNT)
• 2 × Watchdog Timer
• 3 × Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI)
• 1 x Universal Synchronous/Asynchronous Receiver/Transmitter (UART/SPI/I2S)
• 2 × I2C interface with SMBus support
• Keypad scanner supporting up to 6 x 8 matrix (KEYSCAN)
• Die temperature sensor

Protocol Support

• Amazon Sidewalk

HIgh Performance RF

• TX power up to +20 dBm
• -109.5 dBm sensitivity @ 50 kbps, 915 MHz 2GFSK

Wide Operating Range

• 1.71 to 3.8 V single power supply
• -40 °C to +125 °C

Packages

• QFN40 5 mm x 5 mm x 0.85 mm

Secure Vault

• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Hardware Cryptographic Acceleration with DPA Counter measuresfor AES128/256, SHA-1, SHA-2 (up to 256-bit)
• ECC (up to 256-bit) ECDSA, ECDH, and J-PAKE
• True Random Number Generator (TRNG)
• ARM® TrustZone®
• Secure Debug Unlock
• Secure Attestation
• Secure Key Management
• Anti-Tamper